[llvm-dev] unified register set question

Matt Arsenault via llvm-dev llvm-dev at lists.llvm.org
Thu Jan 9 13:29:18 PST 2020

> On Jan 9, 2020, at 16:21, Bagel <bagel99 at gmail.com> wrote:
> On 1/9/20 2:41 PM, Matt Arsenault wrote:
>>> On Jan 9, 2020, at 15:28, Bagel via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>>> My target machine uses the same 64-bit registers for integers and floating point.  Do I have to specify a different register class for floating point
>>> that uses the same set of registers?  Is there a target which does this I can copy?
>> No, you can add any combination of types to the register class. AMDGPU doesn’t distinguish between FP and int registers.
> That's good to know.  However, the register definitions for AMDGPU are over 1000 lines.  I had hoped to learn from something simpler :-)
> My current attempt generates a lot of error messages of the type:
> "Could not infer all types in pattern result!", e.g.:
> /home/bgl/src/llvm-local/llvm/lib/Target/My66000/My66000InstrInfo.td:360:3: error: In STDri: Could not infer all types in pattern result!
>  def ri : LDST_BD<OpCri,
>  ^
> Included from /home/bgl/src/llvm-local/llvm/lib/Target/My66000/My66000.td:24:
> /home/bgl/src/llvm-local/llvm/lib/Target/My66000/My66000InstrInfo.td:370:14: note: instantiated from multiclass
>  defm STD : Store<"std", 0b101011, 0b001011, store>;
>             ^
> STDrr: 	(st GRegs:{ *:[i64 f64] }:$rd, ADDRrr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>

You just need to add an explicit type to this pattern source operand. You probably need to split this into 2 separate store patterns, one for each type.

I do think we should add a size-only pseudo-type for tablegen to handle this kind of case without multiple patterns.


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