[llvm-dev] Correct modelling of instructions with types smaller than the register class

[Dominik Montada via llvm-dev]

Hi Quentin, Hi Amara,

I was following your discussion on D75086 regarding declaring types as 
legal even if they are smaller than the actual register class (e.g. s16 
and gpr32). We are working on a backend which only has 32 and 64-bit 
registers and we recently had a problem regarding exactly this where we 
had to declare G_UNMERGE_VALUES and G_MERGE_VALUES with a smaller type 
of <s32 as legal, even though we don't have a register class that 
matches and instruction selection implicitly sign extends them to s32. 
The reasoning was that for example in the case of G_UNMERGE_VALUES, the 
legalizer widens the source type when widening the destination type, 
which we don't want (as the big type then doesn't fit our registers 
anymore). So we decided to only make sure that the bigger type matches a 
register class and simply allowed smaller types <s32.

What I am gathering now from this discussion is that this is basically 
an incorrect modelling and only works around another problem. Could you 
expand on this in more detail?

I was thinking about implementing some custom legalization which uses 
G_EXTRACT or shifts to get what I want, but G_EXTRACT extracts as many 
bits as the destination type, so I would end up with the same problem 
again. Shifts are also not optimal, since we have a target instruction 
available to extract n bits from a given offset. Is it valid to emit 
target instructions during legalization, i.e. before instruction 
selection, or would the best modelling be to just use the shifts and 
then use some pre-instruction-selection combiner to merge them to the 
desired target instruction?

Best regards,

Dominik

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