[llvm-dev] atomic ops are optimized with incorrect semantics .

[Umesh Kalappa via llvm-dev]

Hi All,

With the "https://gcc.godbolt.org/z/yBYTrd"  case .

the atomic is converted to non atomic ops  for x86 like

from
xchg dword ptr [100], eax
to
mov dword ptr [100], 1

the pass is responsible for this tranformation was instCombine
i.e InstCombiner::visitAtomicRMWInst

which converts the IR like
 %0 = atomicrmw xchg i32* inttoptr (i64 100 to i32*), i32 1 monotonic
to
 store atomic i32 1, i32* inttoptr (i64 100 to i32*) monotonic, align 4

which is valid for relax(monotonic) and release ordering as per the code
out there.

we think that,its the inst lowering issue, where the atomic store was
lowered to non-atomic store here.

to work around we changed our case to strong ordering .

and we are debugging the case with x86 and the same goes with an arm too.

Any suggestions or thoughts on the transformation? , will be helpful to
proceed further.

FYI, the problem persists with LLVM-9, not with the LLVM-8.

Thank you
~Umesh
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