[llvm-dev] [RFC] Case insensitive assembly directives for all targets
David Spickett via llvm-dev
llvm-dev at lists.llvm.org
Wed Feb 5 03:04:44 PST 2020
In response to this issue on Bugzilla, I recently committed changes to make assembly directives case insensitive for generic directives and their aliases, ARM and AArch64. (since those are the targets I have knowledge of)
I realise this was probably a bit too hasty of me, so I'm writing this to gather feedback on how to proceed.
Some concerns were raised that it may be easier to fix projects that aren't using lower case directives. My intent was more to remove our reliance on case in general, which is more an implementation detail than a feature as far as I can tell. Maybe this is not a strong enough argument for change.
No target in llvm uses anything but lower case directives. Some targets supported by GCC/binutils do document mixed case directives, but accept any case.
So my questions for the list are:
* do you agree with the changes so far? (happy to revert if not)
* should the same changes be applied to other targets?
* could there be future situations where a target would need case specific directives?
* Where should this behaviour (whatever it ends up as) be documented? I found  but it's more about extensions than the assembler as such.
LLVM Extensions — LLVM 10 documentation<https://llvm.org/docs/Extensions.html>
SHT_LLVM_ADDRSIG Section (address-significance table) ¶. This section is used to mark symbols as address-significant, i.e. the address of the symbol is used in a comparison or leaks outside the translation unit.
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the llvm-dev