[llvm-dev] TableGen and register banks

[Paul C. Anagnostopoulos via llvm-dev]

I'm beginning to investigate register banks and how a TableGen backend might generate more of the data structures describing them. This is a bit tricky since I am not yet familiar enough with the code generator to understand all the ramifications.

I'm hoping someone can suggest where to start. That is, which data structures would be the simplest to generate. In particular, is there sufficient information in the register info, instruction info, and instruction selection TableGen files to gather the information needed, or is additional information required in xxxRegisterBanks.td file?

Three targets have xxxGenRegisterBankInfo.def files, which contain data structures tagged for generation by TableGen. Three other targets have similar data structures in C++ files. But looking at the AArch64 and AMDGPU files, for example, I see quite a variation in the organization of those data structures.

I think perhaps a need a mentor for this little project.