[llvm-dev] LLVM GPU News Issue #2, December 25 2020

Jakub (Kuba) Kuderski via llvm-dev llvm-dev at lists.llvm.org
Fri Dec 25 14:12:34 PST 2020

Hi folks,

The second issue of LLVM GPU News, a bi-weekly newsletter on all the GPU
things under the LLVM umbrella, is now available at:

I'm also pasting the content below, in case you prefer to read in your
email client.

Happy holidays,


# LLVM GPU News Issue #2, December 25 2020

Welcome to the second issue of LLVM GPU News, a bi-weekly newsletter on all
the GPU things under the LLVM umbrella. This issue covers the period from
December 11 to December 24 2020.

We welcome your feedback and suggestions. Let us know if we missed anything
interesting, or want us to bring attention to your (sub)project, revisions
under review, or proposals. Please see the bottom of the page for details
on how to submit suggestions and contribute.

## Industry News and Conference Talks

*  [Portable Computing Language (PoCL) v1.6 was released](
   The release provides Clang/LLVM 11 support, in addition to the existing
   compatibility down to LLVM 6.0. CUDA backed gained several performance
   optimizations, including use of 32-bit pointer arithmetic for local
   memory, use of static CUDA memory blocks for `__local` blocks and
   function arguments, and loop unrolling heuristic tweaks.
*  [AMD released ROCm v4.0](
   with support for the new MI100 accelerator (HPC GPU) and its new CDNA
   architecture. CDNA is based on the previous GCN architecture and
   backward-compatible with it.

##  LLVM and Clang

### Discussions

*  Nicolai Hähnle posted a proposal on
   [abstractions over SSA form IRs to implement generic analyses](
   This is an attempt to restart the discussion over the previously
   [proposed CfgTraits abstraction](
   that was [reverted in late October 2020](
   The main motivation is to facilitate writing IR-generic analyses that
   operate on both CFG and SSA values, e.g., divergence analysis. The RFC
   comes with a [detailed overview of the C++ generic programming
   and thoughts on how each would fit in the existing LLVM code. Nicolai
   implemented his proposed generic abstractions in a few Phabricator
   *  [D92924: Introduce opaque handles for type erasure.](
   *  [D83089: Based on the handle infrastructure, refactor the dominator
tree with type-erased base classes.](https://reviews.llvm.org/D83089)
   *  [D92925: Introduce an SsaContext context class concept for static
   *  [D92926: Introduce an ISsaContext "global" interface class for
dynamic polymorphism.](https://reviews.llvm.org/D92926)
   *  [D83094: Implement a new analysis (cycle info) written generically as
non-template code.](https://reviews.llvm.org/D83094)

   There are no replies under the thread as of writing.

*  Yaxun (Sam) Liu sent and RFC for
   [unified offloading option for CUDA/HIP/OpenMP](
   The proposal is to make the clang offloading options more concise by
   representing the offloading kind, target, and device architecture with a
   new triple, e.g., `-offload=omp-amd-gfx900`, `-offload=hip-amd-gfx906`.
   Artem Belevich pointed out that making the naming consistent is
   difficult because each offload instance may require an arbitrarily
   complex set of options, and options per individual offload instance may
   differ minimally. Ben Boeckel is concerned about shell quoting rules
   being difficult to get correct with a more complex argument parsing

### Commits

*  [Implement SYCL address space attributes handling.](
   This addresses issues with pointers that have the same address space in
   Clang AST, but different one when lowered to LLVM IR.
*  (In review) [Introduce an OpenMP assumption to ignore possible external
function callers](https://reviews.llvm.org/D93079),
   `omp_no_external_caller_in_target_region`. This function attribute is
   handled by the existing OpenMP target state machine optimization.


### Discussions

* George Mitenkov posted an RFC on
  [converting multi-threaded SPIR-V to the LLVM dialect](
  After the [initial work during the GSoC project](
  that focused on single-threaded code, the next step is to handle
  multi-threaded GPU kernels with synchronization so that they can be
  compiled for CPU execution. George proposes to map each workgroup to a
  CPU thread and subgroups/invocations to SIMD vector operations.
  There are no replies under the thread as of writing.

### Commits

*  [The SPIR-V dialect learned to convert `select+cmp` into GLSL clamp.](
*  SPIR-V (de-)serialization refactoring. The two were
   [split into separate libraries](https://reviews.llvm.org/D91548) and
   de-templated: [\[1\]](https://reviews.llvm.org/D93535), [\[2\]](

## External Compilers

Please submit pointers to your mailing lists, forums, or newsletters if you
want your LLVM- or MLIR-based GPU compiler project to be covered in future
LLVM GPU News issues.

### CUDA

### JuliaGPU

*  Simone Azeglio and Ayaoyao214 asked about
   [overcoming slow scalar operation on GPU arrays](

### LLPC

*  Steven Perron added [support for multi-table descriptor sets](
   This allows for experimentation with more flexible binding models than
   in the Vulkan API that currently guarantees that all resources in the
   same descriptor set will be in the same descriptor table. The patch
   lifts this assumption.

### Mesa

* Michael Tang [committed initial code for a new `spirv_to_dxil` library](
  The plan is to use the Mesa code for WebGPU shader compilation for
  DirectX, using the following translation path: WGSL (WebGPU Shading
  Language) -> SPIR-V (IR from Khronos) -> NIR (Mesa's IR) -> DXIL (DirectX
  Intermediate Language).

### SYCL

Jakub Kuderski
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