[llvm-dev] Register banks

[Gabriel Hjort Åkerlund via llvm-dev]

As far as I have understood it, register banks gives the ability of analyzing 
and making a partial register assignment before selecting the instructions. In 
SelectionISel, instructions are selecting without taking any consideration to 
register classes, which could potentially result in code with excess copying 
between register classes.

This problem can be indeed resolved by adding more abstract forms of register 
banks; this is actually what we currently do for our target. Register banks 
just gives a uniform way of handling it.

Cheers,
Gabriel



-----Original Message-----
From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Paul C. 
Anagnostopoulos via llvm-dev
Sent: den 19 december 2020 17:30
To: llvm-dev at lists.llvm.org
Subject: [llvm-dev] Register banks

What do register banks do that could not have been done by enhancing register 
classes? Is it a matter of separation of concerns?

_______________________________________________
LLVM Developers mailing list
llvm-dev at lists.llvm.org
https://protect2.fireeye.com/v1/url?k=fc04d9d9-a39fe09d-fc049942-861d41abace8-98d2155de8678b7e&q=1&e=671e3fb6-c149-4bcd-b821-ea5743339caf&u=https%3A%2F%2Flists.llvm.org%2Fcgi-bin%2Fmailman%2Flistinfo%2Fllvm-dev
-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/pkcs7-signature
Size: 6320 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20201221/c6116ad9/attachment.bin>