[llvm-dev] How to represent two-address instruction with TableGen?

[Craig Topper via llvm-dev]

You'll need to declare two sources in "ins" like this

```
"add $dst,$src"
(outs GPR64:$dst)
(ins GPR64:$src1, GPR64:$src2)
```

And your pattern will need to be

```
(set GPR64:$dst,(add GPR64:$src1,GPR64:$src2))
```

Then just above your instruction definition you need

```
let Constraints = "$src1 = $dst" in
```

This will tell tell register allocation that they need to be the same
register.


~Craig


On Mon, Dec 14, 2020 at 12:23 AM Zhang via llvm-dev <llvm-dev at lists.llvm.org>
wrote:

> Hi:
> I'm new to LLVM backend and is developing for a custom ISA which
> instruction has two addresses.
> For example:
> add $r0,$1 means r0=r0+r1.
>
> Previously I just declare two operands for add as following:
>
> ```
> "add $dst,$src"
> (outs GPR64:$dst)
> (ins GPR64:$src)
> ```
>
> However when I tried to add ISel patterns to this instruction with the
> following pattern:
>
> ```
> (set GPR64:$dst,(add GPR64:$src,GPR64:$dst))
> ```
>
> I received error:
>
> ```
> In ADDRR: Input operand $dst occurs in pattern but not in operands list!
> ```
>
> Not sure about what I did wrong here, any hint would be much appreciate
>
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