[llvm-dev] Type interference optimization in -gen-dag-isel not working correctly with SDTCisVT and HW modes?

[Paul C. Anagnostopoulos via llvm-dev]

Would you like me to investigate the issues mentioned in your final paragraph?

At 12/5/2020 09:47 PM, Craig Topper wrote:
>There are 3 type checks for i64 in one HW mode and 3 checks for i32 in the other HW mode. One for each operand and one for the result.
>
>I'm probably going to change this to use SDTIntBinOp and get rid of the custom type constraints. That works correctly and generates one type check. It's probably not worth being more specific than that for this case even if it was working correctly. I wanted to bring up the issue since it might be affecting other patterns.
>
>Possibly related, while I was briefly trying to investigate this I noticed that ForceMode in the tablegen backend's TypeInfer class is only ever assigned and never read from. And the DefaultPred std::vector in CodeGenDAGPatterns::ExpandHwModeBasedTypes() is also never read from.
>
>~Craig