[llvm-dev] TableGen: SubTarget SchedWriteRes

[Pietro D'Ettole via llvm-dev]

Ok, finally is working. It was simply due to the fact that when running
assembly code, it was interpreted in ARM coding instead of Thumb2's. My
InstRWs were overriding the latter so no changes could be noticed.
Thanks for your help anyway.

Regards.

Il giorno mer 2 dic 2020 alle ore 22:15 Jason Eckhardt <jeckhardt at nvidia.com>
ha scritto:

> The feature seems to work in general-- I'm using it successfully
> downstream and a number of in-tree back-ends are as well--
> so this may be pilot error. It is difficult to say much more without
> seeing more details of your code.
>
> FWIW, I just checked, and some of the existing ARM (in-tree) scheduling
> descriptions are using InstRW  to override defaults.
> So you can see what is different between your code and those (e.g.,
> ARM/ARMScheduleA9.td). Be sure to check all of your
> boilerplate/plumbing is analogous to one of the existing models.
>
> Also, you can try running the scheduler with debug output against the
> model defined in ARM/ARMScheduleA9.td to make sure you see the appropriate
> overridden
> resources being used for an existing model.
>
> ------------------------------
> *From:* Pietro D'Ettole <progettoiotpolimi2019 at gmail.com>
> *Sent:* Wednesday, December 2, 2020 10:15 AM
> *To:* Jason Eckhardt <jeckhardt at nvidia.com>
> *Subject:* Re: [llvm-dev] TableGen: SubTarget SchedWriteRes
>
> *External email: Use caution opening links or attachments*
> Hi Jason,
>
> Thanks for your help.
> Yes, I already tried them, but even with those overrides added
> instructions use the functional units connected to the WriteALU:SchedWrite
> instead of the one defined by me in the subtarget.
> I was just wondering if the error is either mine or something's not
> properly working in TableGen (I tend to the former, indeed).
> Thank you.
>
> Il giorno mer 2 dic 2020 alle ore 17:00 Jason Eckhardt <
> jeckhardt at nvidia.com> ha scritto:
>
> There isn't enough information in your post to be sure, but did you try
> InstRW subtarget overrides in your sched description?
> def : InstRW<[MyWrALU], (instregex "ANDri$")>;
>
> ------------------------------
> *From:* llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of Pietro
> D'Ettole via llvm-dev <llvm-dev at lists.llvm.org>
> *Sent:* Wednesday, December 2, 2020 8:59 AM
> *To:* llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org>
> *Subject:* [llvm-dev] TableGen: SubTarget SchedWriteRes
>
> *External email: Use caution opening links or attachments*
> Hi everyone,
>
> I was trying to create a model for a subtarget of the ARM processors.
> Though, I've been experiencing some issues. In particular, it seems like
> TableGen does not consider SchedWriteRes defined in the subtarget but only
> the ones defined in the ARM target.
>
> For example, I defined a subtarget SchedWriteRes mapped onto its right
> functional units for ANDri instructions but the instruction does not follow
> what is defined for that SchedWriteRes, but the one defined for the
> WriteALUri in the ARM target.
>
> It may be possible that TableGen does not consider SchedWriteRes defined
> in sub targets?
>
> Regards.
>
>
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