[llvm-dev] Instruction namespace

[Paul C. Anagnostopoulos via llvm-dev]

I'm investigating a TableGen backend function named CodeGenTarget::getInstNamespace, which returns the instruction namespace. It does so by getting the instruction list sorted by enum value (yikes!) and then scanning it linearly for the first instruction whose namespace is not "TargetOpcode".

This suggests that all the machine instructions are in the same namespace. Is that the case? If so, why have a Namespace field in the machine instruction? And even if there is, why not determine the namespace once and store it in the CodeGenTarget instance?

When generating the AMDGPU instruction info, getInstNamespace is called 22 times.