[llvm-dev] Relaxing the restrictions on Machine instruction tied operands

[Brian Leibig via llvm-dev]

Hello,

One of the operand constraints that Tablegen and Machine instrs can impose is tied operands, which means that a def and use in the same instruction must be the same physical register. This allows an operand to be accounted for even if it is not explicitly encoded in the instruction. I am looking at loosening the constraint in a couple ways: having both operands be use (source) operands, and enabling the tied registers to be in different register classes but having the same register number. This is for a target I am writing a backend for, where these registers are pointing to memory, and the instructions using them are transparently performing loads and stores, rather than having the contents of the registers read and written to.

A colleague of mine inquired about such functionality a while ago (http://lists.llvm.org/pipermail/llvm-dev/2019-April/131663.html), and I’ve made some initial steps at implementing this with the patch here: https://reviews.llvm.org/D86586. I will greatly appreciate any feedback or advice on how to implement this, and what in LLVM will need to change in order for this to work.

Thanks,
Brian
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