[llvm-dev] [TableGen] What to do if there are overlapping instruction patterns?

Hal Finkel via llvm-dev llvm-dev at lists.llvm.org
Tue Aug 25 04:51:08 PDT 2020

Hi, Charlotte,

You can set a different decoding namespace for the new instructions. We 
have this for SPE instructions, and this is what we did for QPX 
instructions when those were supported.

In TableGen, you surround the instructions with something like:

let DecoderNamespace = "PairedSingles" in {

and then in Disassembler/PPCDisassembler.cpp, you'll have something like:

   if (STI.getFeatureBits()[PPC::FeaturePairedSingles]) {
     DecodeStatus result =
       decodeInstruction(DecoderTablePairedSingles32, MI, Inst, Address, 
this, STI);
     if (result != MCDisassembler::Fail)
       return result;
   } else if (STI.getFeatureBits()[PPC::FeatureSPE]) {


On 8/25/20 5:00 AM, Charlotte Delenk via llvm-dev wrote:
> I've been working on adding support for a (semi-proprietary) extension 
> for PowerPC called "Paired-Singles". It's a SIMD instruction set 
> supporting various operations on a vector of 2 32-bit floating point 
> numbers.
> The Extension is found in the PowerPC 750CL, modified variants of it 
> are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) 
> and the Nintendo Wii U (Espresso)
> It's been going pretty well so far, however the biggest hurdle I have 
> encountered was that the testsuite is failing because the instruction 
> space for Paired Singles has been reused for ISA 3.1 and VMX.
> Is there a way to disembiguate them further? You can see my current 
> patch at https://reviews.llvm.org/D85137 and it already prevents you 
> from enabling Altivec and Paired Singles at the same time.
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Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory

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