[llvm-dev] Questions about vscale

Renato Golin via llvm-dev llvm-dev at lists.llvm.org
Thu Apr 16 07:31:12 PDT 2020

On Thu, 16 Apr 2020 at 15:15, Hanna Kruppe <hanna.kruppe at gmail.com> wrote:
> Binary portability across
> wildly different vector register sizes is an explicit goal of the ISA,
> adding an exception to this for no good reason would be very
> unfortunate.


> [*] If we settled on requiring VLEN >= 64, we'd still face the same
> problem again if we ever want to add support for vectors elements
> larger than 64b, such as quad-precision floats or 128 bit integers. I
> don't really expect those to be commonly implemented for a long time,
> but once again: it would be great to avoid the need for a separate and
> incompatible target triple if and when such cores become relevant.

Implementation-wise, I don't know, but I think it's a very good point,
at least as an "ultimate goal".

Meanwhile, there could be something "interim" to be done for the
particular cases where you do have an existing hardware
implementation, that doesn't need a whole new ABI?


PS: The float ABI on Arm32 was a nightmare, and I'm glad we're
(mostly) past those days. I wouldn't want to force anyone to do it
again. :)

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