[llvm-dev] RFC: Promoting experimental reduction intrinsics to first class intrinsics
Amara Emerson via llvm-dev
llvm-dev at lists.llvm.org
Wed Apr 8 12:40:04 PDT 2020
> On Apr 8, 2020, at 9:54 AM, Nikita Popov <nikita.ppv at gmail.com> wrote:
> On Wed, Apr 8, 2020 at 6:59 AM Amara Emerson via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
> It’s been a few years now since I added some intrinsics for doing vector reductions. We’ve been using them exclusively on AArch64, and I’ve seen some traffic a while ago on list for other targets too. Sander did some work last year to refine the semantics after some discussion.
> Are we at the point where we can drop the “experimental” from the name? IMO all target should begin to transition to using these as the preferred representation for reductions. But for now, I’m only proposing the naming change.
> There's still a couple of open issues that I'm aware of:
> 1. fmin/fmax reductions without nnan flag do not work. IR expansion code assumes that these always use FMF. It's also under-documented what their exact behavior is, though I assume it should match llvm.minnum/llvm.maxnum semantics to be most useful.
I think without the nnan flag, the semantics should be equivalent to an ordered (i.e. serialized) reduction of llvm.fmin/fmaxnum. Any issues with this?
> 2. SDAG legalization support for float softening is missing.
> 3. SDAG legalization for ordered reductions is missing.
> I think point 1 is the only real blocker here, the rest can be avoided by force-expanding these cases in IR.
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