[llvm-dev] Matching the same chain multiple times?

[Thomas Lively via llvm-dev]

Update: I tried changing the check to be that there is only one user rather
than only one use and that got the pattern to match, but the mem argument
on the resulting machine instruction has four copies of the input chain. I
would like them to be deduplicated (since there is really just one load),
so I continue to suspect that there is a better way to go about this.

On Tue, Sep 17, 2019 at 5:41 PM Thomas Lively <tlively at google.com> wrote:

> Hi all!
>
> I'm trying to do instruction selection on a pattern like the following:
>
> Pat<(v4i32 (build_vector (i32 (load I32:$addr)), (i32 (load I32:$addr)),
> (i32 (load I32:$addr)), (i32 (load I32:$addr))))), (LOAD_SPLAT 0, 0,
> I32:$addr)>;
>
> Note that all those loads are actually the same load. This fails to match
> as expected because of the OPC_EmitMergeInputChains operation. There is a
> check at
> https://github.com/llvm/llvm-project/blob/20b52c33ba3960340ecf326314517091b8ec98f4/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp#L3304 that
> the chain to be merged has only one use, but in this case it has four uses,
> all of which are matched in the same pattern.
>
> I've tried updating the condition to allow this, but I haven't had any
> luck so far. Is there any other way to perform the match I want?
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190917/e84b9749/attachment.html>