[llvm-dev] Register allocation constraints
黄岚之观 via llvm-dev
llvm-dev at lists.llvm.org
Sat Oct 12 02:47:29 PDT 2019
I have a problem during my development of a backend. There are some
target instructions with multiple outputs, for example an instructionX with
2 inputs and 2 outputs:
def1, def2 = InstructionX op1, op2
The defs above must be allocated in consecutive target physical registers.
Is it possible to describe the constraints with tablegen and let the
register allocator get all the things done or is regalloc hints related api
designed just to solve the problem? Any suggestions?
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