[llvm-dev] LiveInterval error with 2 dead defs

[Krzysztof Parzyszek via llvm-dev]

The associated patch caused a compilation problems on Hexagon: https://bugs.llvm.org/show_bug.cgi?id=43302

The splitting of a live interval should not be done automatically upon creation.  Calling LIS->getInterval(Reg) should not go around changing the code behind the scenes.

There is already a function “splitSeparateComponents” that does that.  It should be added where it’s missing.

--
Krzysztof Parzyszek  kparzysz at quicinc.com<mailto:kparzysz at quicinc.com>   AI tools development

From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Quentin Colombet via llvm-dev
Sent: Monday, September 9, 2019 7:17 PM
To: Arsenault, Matthew <Matthew.Arsenault at amd.com>
Cc: llvm-dev <llvm-dev at lists.llvm.org>
Subject: [EXT] Re: [llvm-dev] LiveInterval error with 2 dead defs

Hi Matt,

The expectation is that each LiveInterval should only have values that are connected somehow, otherwise these should be split into different liveinterval.
I don’t think anything bad would happen when this assumption is broken (hence why it looks fine in your example), but it certainly puts needless constraints on the live-ranges.

I’m guessing Jakob added that check to make sure the splitting mechanism would create one live-range per connected component.

If you’re hitting that problem that means you miss somewhere a call to ConnectedVNInfoEqClasses::Distribute.

Cheers,
-Quentin

On Sep 9, 2019, at 3:36 PM, Arsenault, Matthew <Matthew.Arsenault at amd.com<mailto:Matthew.Arsenault at amd.com>> wrote:

Hi,

I’m hitting a machine verifier error in a trivial testcase which I don’t understand. There are 2 dead defs of the same register:
---
name:            multiple_connected_compnents_dead
tracksRegLiveness: true
body:             |
  bb.0:
    dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec

...

The live intervals look OK to me with 1 valno per instruction, for the life of the instruction like I would expect. The verifier does not like it however:

$ llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -o - -verify-misched foo.mir

# Before machine scheduling.
********** INTERVALS **********
%0 [16r,16d:1)[32r,32d:0)  0 at 32r 1 at 16r weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function multiple_connected_components_dead: NoPHIs, TracksLiveness

0B           bb.0:
16B          dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
32B          dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec

# End machine code for function multiple_connected_components_dead.

*** Bad machine code: Multiple connected components in live interval ***
- function:    multiple_connected_components_dead
- interval:    %0 [16r,16d:1)[32r,32d:0)  0 at 32r 1 at 16r weight:0.000000e+00
0: valnos 0
1: valnos 1
LLVM ERROR: Found 1 machine code errors.

What is the problem here?

-Matt

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20191007/85d47d54/attachment.html>