[llvm-dev] Adding support for vscale
Robin Kruppe via llvm-dev
llvm-dev at lists.llvm.org
Tue Oct 1 00:08:26 PDT 2019
Hello Jacob and Luke,
First off, even if a dynamically changing vscale was truly necessary for
RVV or SV, this thread would be far too late to raise the question. That
vscale is constant -- that the number of elements in a scalable vector does
not change during program execution -- is baked into the accepted scalable
vector type proposal from top to bottom and in fact was one of the
conditions for its acceptance (runtime-variable type sizes create many more
headaches which nobody has worked out how to solve to a satisfactory degree
in the context of LLVM). *This* thread is just about whether vscale should
be exposed to programs in the form of a Constant or as an intrinsic which
always returns the same value during one program execution.
Luckily, this is not a problem for RVV. I do not know anything about this
"SV" extension you are working on so I cannot comment on that, but I'll
sketch the reasons for why it's not an issue with RVV and maybe that helps
you with SV too. As mentioned above, this is tangential to the focus of
this thread, so if you want to discuss further I'd prefer you do that in a
The dynamically-changing VL is a kind of predication in that it limits
processing to a subset of lanes, and like masks it can just be another SSA
value that is an input to the computations it affects. You may be aware of
Simon Moll's vector predication (previously: explicit vector length)
proposal which does just that. In contrast, the vscale concept is more
about how many elements a vector register contains, regardless of whether
some operations process only a subset of them. In RVV terms that means it's
related not to VL but more to VBITS, which is indeed a constant (and has
been for many months).
The only dynamic thing about "how many elements are there in a vector
register" is that varying the width of the elements (8b, 16b, etc.) and the
length multiplier (grouping together 1/2/4/8 registers) causes a
predictable, relative increase or decrease (x2, x8, x0.5, etc.) of the
number of elements, regardless of the specific value of VBITS. But this is
perfectly compatible with a constant vscale because vscale only is the
unknown-at-compile-time *factor* in the size of a scalable vector type.
Varying the other components, the compile-time-constant factor and the
element type, results in scalable vectors with different *relative* sizes
in exactly the same way we need to handle RVV's element width and LMUL
concepts. For example <vscale x 4 x i16> has four times as many elements
and twice as many bits as <vscale x 1 x i32>, so it captures the
distinction between a SEW=16,LMUL=2 vtype setting and a SEW=32,LMUL=1 vtype
On Mon, 30 Sep 2019 at 23:53, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Tuesday, October 1, 2019, Jacob Lifshay <programmerjake at gmail.com>
>> On Mon, Sep 30, 2019 at 2:30 AM Sander De Smalen via llvm-dev
>> <llvm-dev at lists.llvm.org> wrote:
>> > I've posted two patches on Phabricator to add support for VScale in
>> > A brief recap on `vscale`:
>> > The scalable vector type in LLVM IR is defined as `<vscale x n x m>`,
>> to create types such as `<vscale x 16 x i8>` for a scalable vector with at
>> least 16 bytes. In the definition of the scalable type, `vscale` is
>> specified as a positive constant of type integer that will only be known at
>> runtime but is guaranteed to be constant throughout the program.
> Ah. Right. There is something known as data-dependent fail-on-first,
> which does not match with the assertion that vscale will be constant.
> Yes any given vector would be vscale long and it is good to be able to
> runtime declare such vectors: loops in assembler may be generated which
> sets VL (a Control Status Register declaring the number of elements to be
> processed in any given loop iteration)
> However for e.g memcpy or strcpy or anything else which is *not* fixed
> length and not even the program knows how long the vector will be, there is
> data-dependent fail-on-first.
> A related thread goes through this, pay attention to Stephen's questions
> and it becomes clear:
> A link to ARM SVE ffirst capability is also proved in that thread. Yes,
> SVE has ffirst although it is a SIMD variant rather than one that affects
>> RISC-V RVV explicitly allows changing VL (which I am assuming is the
>> same as vscale) at runtime, so VL wouldn't be a constant.
> This would be good to clarify, Sander. On first reading it seems to me
> that vscale is intended to be the actual full vector size, not related to
> Regardless, setting it even as *runtime* constant seems to be a red flag.
> What is vscale intended for, and how does it relate to Cray-like Vector
>> Additionally, we (libre-riscv) are working on a similar scalar vectors
>> ISA called SimpleV that also allows changing VL at runtime and we are
>> planning on basing it on LLVM's scalable vector support.
> Both SV and RVV are based on Cray VL which is a runtime global CSR setting
> the number of elements to be processed in any given vector loop.
> The difference is that RVV *requests* a VL and is arbitrarily *allocated*
> an actual VL (less than or equal to the requested VL), where in SV you get
> exactly what is requested and if overallocated an illegal instruction is
>> >  https://reviews.llvm.org/D68202
>> >  https://reviews.llvm.org/D68203
>> Jacob Lifshay
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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