[llvm-dev] Question on pattern matching extractelt

Sebastien Le Duc via llvm-dev llvm-dev at lists.llvm.org
Thu Nov 28 08:51:20 PST 2019

I have an issue with pattern matching. 
I have the following SelectionDAG: 
t13: i32 = extract_vector_elt t2, Constant:i64<1> 

That I am trying to match with the following pattern: 

def : Pat<(extractelt (v4i16 SingleReg:$v), 1), (SRADd1 SingleReg :$v, (i64 16))>; 

But for some reason the pattern does not match. 
It seems to be due to the fact extract_vector_elt's result type is i32 (because i16 is not a legal type on our processor), but according to the comment in ISDOpcodes.h, it is allowed for EXTRACT_VECTOR_ELT to have a result type larger than the element type of the vector, so I would expect to be able to match such pattern. 

I tried specifying the result type in the pattern: 
def : Pat<(i32 (extractelt (v4i16 SingleReg:$v), 1)), (SRADd1 SingleReg :$v, (i64 16))>; 

But in that case I get a tblgen error: 

possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records). 
anonymous_1188: (extractelt:{ *:[] } SingleReg:{ *:[] }:$v, 0:{ *:[i64] }) 

Is there anyway to match such pattern? 

Thanks in advacne! 

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