[llvm-dev] Question about physical registers in ISel

Thomas Lively via llvm-dev llvm-dev at lists.llvm.org
Mon Nov 18 18:21:34 PST 2019

Hi all,

I need to figure out why InstrEmitter::EmitMachineNode assumes that when
the number of outputs of a MachineSDNode is greater than the number of defs
in the corresponding MCInstrDesc, the outputs in the difference will be
placed into physical registers as opposed to virtual registers.

The specific line in question is:
    bool HasPhysRegOuts = NumResults > NumDefs &&

Where NumResults is the number of outputs in the MachineSDNode and NumDefs
comes from the MCInstrDesc and ultimately the TableGen definition of the
instruction. I do not know why this assumption is made or what code depends
on it, but it is over 12 years old:

The context for this question is that I am trying to implement an
instruction for the WebAssembly backend that returns a variable number of
operands. I am following the example of ARM's load multiple instructions,
but this assertion in the instruction emitter is causing problems because
WebAssembly, unlike ARM, does not use physical registers at all. Also,
almost all WebAssembly instructions have an implicit def of the register
that represents the argument stack, so II.getImplicitDefs() is necessarily

I am open to ideas about the best way forward. I am currently thinking that
if this assumption is important for most targets, I might need to add a new
bit to MCInstrDesc to disable this assumption.
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