[llvm-dev] Understanding targets

[Gaier, Bjoern via llvm-dev]

Woah! Thank you so much! That helped me a lot! Now I understand the entire subject a better then before.

-----Original Message-----
From: Simon Atanasyan <simon at atanasyan.com>
Sent: 14 November 2019 10:46
To: Gaier, Bjoern <Bjoern.Gaier at horiba.com>
Cc: Robinson, Paul <paul.robinson at sony.com>; llvm-dev at lists.llvm.org
Subject: Re: Understanding targets

Hi,

1. Here by architecture I mean instruction set architecture (ISA) [1].
In extremely simplified form ISA can be considered a set of machine instructions which can be handled by CPU.

2. Intel, ARM, MIPS etc design various ISAs. Intel designs and manufactures CPUs. AMD uses almost the same instruction set as Intel but uses different "internal" design of CPUs and manufactures them by itself too. ARM, MIPS and some other companies only design CPUs. ARM and MIPS processors are manufactured by other companies like Mediatek or Qualcomm for example. Sometimes chipmakers produce CPU with "canonical" design. Sometimes they add extensions. New instructions for example.

2. Sometimes CPU name almost directly points to supported ISA. It's true for Intel CPUs. For ARM and MIPS it's more difficult. There no ISA named "Qualcomm Snapdragon 820" and you have to look as documentation to get know that this chip supports ARMv8 ISA. MIPS
R3000 [2] implements MIPS I ISA [3].

3. RISC is an abbreviation for "reduced instruction set computer" [4].
It covers a large set of ISAs designed by different companies. MIPS in particular. RISC-V (supported by LLVM) is an open-source hardware instruction set architecture based on "reduced instruction set computer" principles [5]. MIPS 1 is a RISC ISA, RISC-V is a RISC ISA too. But MIPS 1 is not equal to RISC-V as well as MIPS 1 is not equal to SPARC.

4. Some ISA defines floating point instructions, some other does not do that. CPU might support most part of ISA but does not support floating point instructions. You need to refer CPU documentation. For example, if your CPU supports MIPS32 R2 ISA (which defines FPU instructions), but does not have FPU, you can specify that and request emulation of FPU by the following Clang options: -mips32r2 -msoft-float.

[1] https://en.wikipedia.org/wiki/Instruction_set_architecture
[2] https://en.wikipedia.org/wiki/R3000
[3] https://en.wikipedia.org/wiki/MIPS_architecture#MIPS_I
[4] https://en.wikipedia.org/wiki/Reduced_instruction_set_computer
[5] https://en.wikipedia.org/wiki/RISC-V

On Thu, Nov 14, 2019 at 10:11 AM Gaier, Bjoern <Bjoern.Gaier at horiba.com> wrote:
> So the R3000 is a "MIPS CPU"? What does that actually mean? Is the architecture MIPS? Or the producer? When I go to Wikipedia I see MIPS as the designer, so I take it is like saying "Intel CPU" or "AMD CPU" but that does not tell me anything about the assembly instruction it uses, right?
> But then also I see as Design "RISC", as I understood it describes the assembly instructions? But why would I tell Clang to target "mips1" when the design of the R3000 is RISC? Why isn't RISCV correct then? Or RISC1 or so...
>
> Also how does that influence floating point arithmetic? I often heard that those are separated processors FPUs(?). So could it be, that there is an additional processor besides the processor I know about? Like R3000 + FPU? Wouldn't had Clang or any other compiler to know about such a construct or is that not the case?

--
Simon Atanasyan
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