[llvm-dev] Understanding targets
Tim Northover via llvm-dev
llvm-dev at lists.llvm.org
Thu Nov 14 01:51:10 PST 2019
On Thu, 14 Nov 2019 at 07:11, Gaier, Bjoern via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Both of your answers helped me a lot! So If I understand it correctly, Clang knows what 'mips1' and 'mips5' are - but can't generate code for it? Why is it like that?
> I actually have a more in general questions about processors... If this is the wrong place for it, please ignore it, I'm just a bit confused.
> So the R3000 is a "MIPS CPU"? What does that actually mean? Is the architecture MIPS? Or the producer?
Both. MIPS (the company) developed the MIPS architecture, specifying
what instructions would exist and how they would be encoded. Then MIPS
(the company) designed CPUs that implemented this MIPS architecture.
One of those CPUs is R3000. Other companies and individuals have also
designed CPUs that implement the MIPS architecture.
> When I go to Wikipedia I see MIPS as the designer, so I take it is like saying "Intel CPU" or "AMD CPU" but that does not tell me anything about the assembly instruction it uses, right?
Right, or at least not intrinsically. In practice MIPS (the company)
revolved around their instruction set so it would be very odd if it
> But then also I see as Design "RISC", as I understood it describes the assembly instructions?
RISC is an adjective describing certain instruction sets (see
lines have gotten a bit blurry and debatable, but broadly RISC
instruction sets tend to usemore, simpler instructions to do the work.
Where x86 has "load from memory and multiply by this register" as a
single instruction, RISC instruction sets would have a separate load
instruction followed by a multiply instruction. They also tend to have
more, and more general purpose registers.
So RISC on its own doesn't tell you what instructions are supported or
what their encodings are.
> But why would I tell Clang to target "mips1" when the design of the R3000 is RISC?
The R3000 implemented version 1 of the MIPS architecture. As far as
the compiler is concerned, all CPUs implementing the mips1 version of
the instruction set are roughly the same. They all support the same
instructions and code compiled for one of them will run on the others.
Of course there are sometimes differences in how many cycles each
instruction takes to run and so on. And to support that Clang would
add a separate R3000 CPU that can be targeted.
> Why isn't RISCV correct then? Or RISC1 or so...
RISC-V is categorically different from RISC. RISC-V *is* a separate
instruction set architecture (with specific instructions and
encodings), named because it's the 5th generation of RISC
architectures by some reckoning. There weren't any RISC-I through
> Also how does that influence floating point arithmetic? I often heard that those are separated processors FPUs(?).
They used to be, back in the 80s and 90s, but were fairly quickly
integrated into the main CPU. Older RISC designs (like MIPS & ARM)
treat them like they're separate in the instruction set even after
they got integrated. They had separate instructions for dealing with
all kinds of coprocessors, and one of those kinds is the FPU, which
then got fossilized.
> So could it be, that there is an additional processor besides the processor I know about? Like R3000 + FPU? Wouldn't had Clang or any other compiler to know about such a construct or is that not the case?
In theory, yes. In practice a CPU either has the FPU corresponding to
its era or it doesn't. Clang assumes it does but lets you override
this with some options (-msoft-float, -msingle-float)
More information about the llvm-dev