[llvm-dev] strange output from llvm-mc

s nedunuri via llvm-dev llvm-dev at lists.llvm.org
Sun May 12 19:24:38 PDT 2019

It looks to me like llvm-mc is doing something strange. Eg:

              echo "pop ebp" | llvm-mc -assemble -arch=x86 -filetype=obj -o

Now disassembling temp.bin:

$ llvm-objdump -disassemble -x86-asm-syntax=intel -section-headers temp.bin

temp.bin:       file format COFF-i386

Disassembly of section .text:

0000000000000000 .text:

       0:       8f 05 00 00 00 00       pop     dword ptr [0]


Idx Name          Size      Address          Type

  0 .text         00000006 0000000000000000 TEXT

  1 .data         00000000 0000000000000000 DATA

  2 .bss          00000000 0000000000000000 BSS

Llvm-mc is generating the opcode 8f, which is why its getting disassembled
as “pop dword ptr [0]”. Looking at the intel reference for pop you’ll see
that the “8f” opcodes are for pops to memory locations, not to registers.
If I create a file "simple.s" containing "pop ebp" using a different
assembler (eg nasm) generates the correct opcode (5D):

$ nasm -f win32 simple.s -l simple.lst

$ more simple.lst

     1 00000000 5D                      POP EBP

Anyone know what's going on? Did I miss a flag somewhere

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190512/0d3886a6/attachment.html>

More information about the llvm-dev mailing list