[llvm-dev] Spilling multiple individual instructions not supported in [Target]InstrInfo::storeRegToStackSlot()? (error: <<Assertion `itr != mi2iMap.end() && "Instruction not found in maps."' failed.>>)

Tom Stellard via llvm-dev llvm-dev at lists.llvm.org
Fri May 3 19:41:26 PDT 2019

On 05/03/2019 06:13 PM, Alex Susu via llvm-dev wrote:
>   Hello.
>     Could you please tell me: is it not allowed to create 2 or more individual (that is, not bundled) instructions in ConnexInstrInfo::storeRegToStackSlot()? Such a thing was possible with an older version, LLVM 3.9 from Jul 2016, but with a very recent version of LLVM from Mar 2019 (SVN revision 357222) it seems it's not possible anymore.
>     For example, when I add 1 NOP and 1 STORE instruction (I can even create more than 2 instructions) at iterator I in ConnexInstrInfo::storeRegToStackSlot() I get the following error:
>       <<Assertion `itr != mi2iMap.end() && "Instruction not found in maps."' failed.>>
>     But if I create only 1 instruction then everything is OK.
>      I found some info from 2017 that supports my reasoning at https://lists.llvm.org/pipermail/llvm-dev/2017-February/110281.html where they write:
>       - "This does make the assumption that storeRegtoStackSlot only inserts a single
> instruction. From what I can see, that is true for all in-tree backends."
>       - "modify storeRegToStackSlot to return the number of MachineInstr inserted and use that value when marking instructions as FrameSetup. This is more invasive, as it will affect all in tree and out-of-tree backends."
>     Please let me know what is the exact situation now in LLVM: can't we create more than 1 individual instruction in 1 call of [Target]InstrInfo::storeRegToStackSlot()?

I think this is still the case that you are only allowed to add 1 instruction.
The AMDGPU backend[1] works around this by emitting a single pseudo
instruction during register allocation and then expanding it to multiple
instructions in a later pass.


[1] https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp#L915

>   Thank you,
>     Alex
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