[llvm-dev] Question about TableGen RegisterClass definition

[JinGu Kang via llvm-dev]

Hi All,

I have a question about TableGen RegisterClass definition.

I need to map different size of MVTs into a register class as below.

def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...>

When I look at TableGen and CodeGen, it looks the types are used as following:

1. MCRegisterClass's RegSize and Alignment
2. SpillSize in TableGen
3. Type constraint for instruction pattern matching

>From my opinion, it seems it is possible to do it... but I am not 100% sure... If anyone has information about it, please give me comment.

Thanks


JinGu Kang
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