[llvm-dev] RFC: Complex in LLVM

[David Greene via llvm-dev]

Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> writes:

> Vectorization must know the data layout: whether we have vectors (r1,
> i1, r2, i2...) or (r1, r2, ...), (i1, i2, ...).  These two approaches
> are not compatible.  If you have vector registers that can hold 8
> floats, with the first approach you can load 4 complex numbers in a
> single instruction, then multiply by another 4 numbers, and store.
> With the second approach, the minimum unit of work is 8 numbers, and
> each input to the multiplication has to be loaded in two instructions,
> loading real and imaginary parts from two separate locations.  On most
> architectures the second approach would be vastly superior, but the
> v4c32 type mentioned in the RFC suggests the first one.

That's true.  I was assuming that if the vectorizer wants to extract
reals from a vector of complex, we'd need an operation to do that that
results in a different vector type (say, two v4c32 -> one v8f32).  It's
a special kind of shufflevector.  The reverse operation is also useful.

> In addition to that, we shouldn't limit complex types to floating
> point only.  What we care about is keeping the "ac-bd" together, not
> what type a,b,c,d are.

Can you give some examples of non-FP types where a higher-level
representation would be useful?

                        -David