[llvm-dev] [RFC] Vector Predication

Simon Moll via llvm-dev llvm-dev at lists.llvm.org
Thu Jan 31 07:58:35 PST 2019


There is now an RFC for a roadmap to native vector predication support 
in LLVM and a prototype implementation:


The prototype demonstrates:

-  Predicated vector intrinsics with an explicit mask and vector length 
parameter on IR level.
-  First-class predicated SDNodes on ISel level. Mask and vector length 
are value operands.
-  An incremental strategy to generalize 
PatternMatch/InstCombine/InstSimplify and DAGCombiner to work on both 
regular instructions and EVL intrinsics.
-  DAGCombiner example: FMA fusion.
-  InstCombine/InstSimplify example: FSub pattern re-writes.
-  Early experiments on the LNT test suite (Clang static release, O3 
-ffast-math) indicate that compile time on non-EVL IR is not affected by 
the API abstractions in PatternMatch, etc.

We’d like to get your feedback, in particular on the following to move 

-  Can we agree on EVL intrinsics as a transitional step to predicated 
IR instructions?
-  Can we agree on native EVL SDNodes for CodeGen?
-  Are the changes to InstCombine/InstSimplify/DAGCombiner and utility 
classes that go with it acceptable?



Simon Moll
Researcher / PhD Student

Compiler Design Lab (Prof. Hack)
Saarland University, Computer Science
Building E1.3, Room 4.31

Tel. +49 (0)681 302-57521 : moll at cs.uni-saarland.de
Fax. +49 (0)681 302-3065  : http://compilers.cs.uni-saarland.de/people/moll

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