[llvm-dev] [8.0.0 Release] rc1 has been tagged

[Bruce Hoult via llvm-dev]

In https://llvm.org/svn/llvm-project/llvm/branches/release_80 I find
that RISCV is still in LLVM_EXPERIMENTAL_TARGETS_TO_BUILD. not
LLVM_TARGETS_TO_BUILD. I thought people had agreed to change that in
this release?

There are also at least a couple of fairly important patches that it
would be good to get back-ported into the release branch if possible

r352171 | asb | 2019-01-24 21:11:34 -0800 (Thu, 24 Jan 2019) | 12 lines
[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M

r352169 | asb | 2019-01-24 21:04:00 -0800 (Thu, 24 Jan 2019) | 24 lines
[RISCV] Custom-legalise 32-bit variable shifts on RV64


Others that would be good, but perhaps not so important to get in:

r352240 | asb | 2019-01-25 13:06:47 -0800 (Fri, 25 Jan 2019) | 7 lines
[RISCV] Add another potential combine to {double,float}-bitmanip-dagcombines.ll

r352237 | apazos | 2019-01-25 12:22:49 -0800 (Fri, 25 Jan 2019) | 3 lines
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI

r352211 | asb | 2019-01-25 08:04:04 -0800 (Fri, 25 Jan 2019) | 6 lines
[RISCV][NFC] s/f32/f64 in double-arith.ll

r352199 | asb | 2019-01-25 06:33:08 -0800 (Fri, 25 Jan 2019) | 8 lines
[RISCV] Add tests to demonstrate bitcasted fneg/fabs dagcombines

r352008 | apazos | 2019-01-23 18:31:23 -0800 (Wed, 23 Jan 2019) | 9 lines
[RISCV] Set isReMaterializable for ORI, XORI

On Wed, Jan 23, 2019 at 4:50 PM Hans Wennborg via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
>
> Dear testers,
>
> 8.0.0-rc1 was just tagged (from the branch at r351980).
>
> It took a little longer than planned, but it's looking good.
>
> Please run the test script, share your results, and upload binaries.
>
> I'll get the source tarballs and docs published as soon as possible,
> and binaries as they become available.
>
> Thanks,
> Hans
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