[llvm-dev] [System Model] MC layer vs. Target layer

[David Greene via llvm-dev]

Following the discussion around the system model RFC [1], I'm working on
porting our model over to master.  The model was developed quite some
time ago against a much older version of LLVM and I'm taking the
opportunity to modernize it.

The MC layer didn't even exist when we first developed the model and now
I am wondering about the split in responsibilities between the MC and
Target layers.  We have things like MCRegisterInfo/TargetRegisterInfo
and MCSchedModel/TargetSchedModel.

The RegisterInfoEmitter in TableGen seems to emit tables for both
MCRegisterInfo and TargetRegisterInfo and SubtargetEmitter emits tables
for both MCSchedModel and TargetSchedModel.  Our code enhances
SubtargetEmitter to emit tables for TargetMemoryModel and some other
things to support it.

What is the intent/purpose of multiple classes and emitting multiple
tables for what seems like singular concepts (scheduling info, register
info)?  I'm wondering what, if anything I should delegate to the MC
layer regarding a system model and what is appropriate for the Target
layer.  Maybe I don't even need an MC layer model though I have a
sneaking suspicion that eventually we'll want one.

Any advice is very welcome!

                       -David

[1] https://lists.llvm.org/pipermail/llvm-dev/2018-October/127319.html