[llvm-dev] Unfolded additions of constants after promotion of @llvm.ctlz.i16 on SystemZ

Jonas Paulsson via llvm-dev llvm-dev at lists.llvm.org
Fri Feb 8 09:20:15 PST 2019


SystemZ supports @llvm.ctlz.i64() natively with a single instruction 
(FLOGR), and lesser bitwidth versions of the intrinsic are promoted to i64.

For some reason, this leads to unfolded additions of constants as shown 

This function:

define i16 @fun(i16 %arg) {
   %1 = tail call i16 @llvm.ctlz.i16(i16 %arg, i1 false)
   ret i16 %1

,gives this optimized DAG as input to instruction selection:

SelectionDAG has 15 nodes:
   t0: ch = EntryToken
                 t2: i32,ch = CopyFromReg t0, Register:i32 %0
               t10: i32 = and t2, Constant:i32<65535>
             t16: i64 = zero_extend t10
           t17: i64 = ctlz t16
         t22: i64 = add t17, Constant:i64<-32>
       t20: i32 = truncate t22
     t15: i32 = add t20, Constant:i32<-16>
   t7: ch,glue = CopyToReg t0, Register:i32 $r2l, t15
   t8: ch = SystemZISD::RET_FLAG t7, Register:i32 $r2l, t7:1

It seems that SelectionDAG::computeKnownBits() has a case for ISD::CTLZ, 
and it seems to figure out that the high bits of t17 are zero, as expected.

t17 is guaranteed to have a value between 48 and 64, so there could not 
be any overflow here, even though I am not sure if that's the problem or 
not... Should DAGCombiner::visitADD() handle this, or perhaps 

Thanks for any help,


More information about the llvm-dev mailing list