[llvm-dev] [RFC] Vector Predication

Luke Kenneth Casson Leighton via llvm-dev llvm-dev at lists.llvm.org
Tue Feb 5 05:26:16 PST 2019

On Tue, Feb 5, 2019 at 1:19 PM Simon Moll <moll at cs.uni-saarland.de> wrote:
> On 2/5/19 2:00 PM, Bruce Hoult wrote:
> > On Tue, Feb 5, 2019 at 4:28 AM Simon Moll <moll at cs.uni-saarland.de>

> Ok. I am just poking around a little to see whether something like
> llvm.evl.setvl
> (https://lists.llvm.org/pipermail/llvm-dev/2019-February/129973.html)
> would be compatible with your solution for MVL configuration in RVV

 it looks good to me as far as SV is concerned (however do bear in
mind that in SV, AVL goes from *1* to MVL, it is *not* possible to set
SV's AVL or MVL to zero).

 for SIMD architectures without predication masks, for all but the
last of a loop they could return the nearest power of 2 that fits an
available SIMD instruction width, and do "corner-case-nonsense" and/or
gather/scatter for when requested vl is less than the smallest
available SIMD width.

 for SIMD architectures *with* predication masks, they could return
the largest (nearest, most comfortable) power of 2 and use
extra-masking (end-masking) for the end of the loop (when requested_vl
< smallest available SIMD width)


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