[llvm-dev] Instruction with same mnemonic but different encoding
Siddharth Shankar Swain via llvm-dev
llvm-dev at lists.llvm.org
Mon Feb 4 04:35:28 PST 2019
Is there any way in llvm where the assembler can handle instructions with
same name mnemonics but with different encodings? when there is slight
change in the architecture. I came across the suggestion to use different
decodernamespace but that doesn't seem to work. Please guide.
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