[llvm-dev] ABI-specific Stack Pointer Register?

Reid Kleckner via llvm-dev llvm-dev at lists.llvm.org
Wed Dec 4 12:45:10 PST 2019

>From past conversations, I was under the impression that GHC functions are
really "stackless", they use CPS: they run, perform some computation,
update the passed-in virtual stack registers, and then return with some
sort of tail call, preserving and updating the set of registers which were
passed in. Why does it matter if LLVM spills intermediate data to the
architectural stack if it clears it all off on exit?

Regarding the feasibility of it, I think it's actually feasible. Depending
on how radical the changes you need are, I would recommend subclassing the
TargetFrameLowering classes and providing new implementations of
emitPrologue, emitEpilogue, and getFrameIndexReference. The X86
emitPrologue codepath is already very, very complicated, and handles far
too many special cases. Much of the complexity comes from CFI, and that
wouldn't be a concern with an alternative stack.

On Wed, Dec 4, 2019 at 12:16 PM Kavon Farvardin via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Hi,
> In the runtime system for GHC Haskell, the stack pointer register is not
> the same as the one defined by the operating system ABI, and it's difficult
> for GHC to change that. Following the example of CoreCLR in LLVM, it seems
> one way to remedy this situation is to define a new ABI (i.e., a new
> llvm::Triple::EnvironmentType ) and modify the code generator as-needed to
> respect to our ABI, through our own definition of an MCAsmInfo class for
> each architecture, etc.
> My question is: how feasible is it to extend MCAsmInfo with an override
> for the stack pointer register and have that fact be respected by the code
> generator?
> Currently, MCAsmInfo only specifies the stack direction, and from what
> I've seen in the x86 backend (and instruction selection), RSP is assumed to
> be the stack-pointer register and is hard-coded in a number of places.
> Any other suggestions of alternate ways to achieve this change in LLVM
> code generation for both ARM64 and x86-64 are welcomed!
> Thanks,
> Kavon
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