[llvm-dev] [MachineScheduler] Is there any plan to support machine scheduling across call?

[Zeson Wu via llvm-dev]

Hi, all.

I have a question about the machine scheduler support of call instruction.

For now SDNode scheduler is made to keep instructions in source order when
enable machine scheduler as default scheduler. But machine scheduler can
not schedule call instruction so that the case as following can cause
spills(more register usage) in prologue because the calculation can not be
scheduled together and the source sequence is not efficient(reg pressure
and latency) . Is there any good solution to fix this? Is there any plan to
support machine scheduling across call?

```
int t;
__attribute__((noinline)) void g() {t+=3;}
int foo(int m, int n) {

        int t = m *3;
        int q = m/3;
        int q1 = m/31;
        int q2 = m/32;
        int q3 = m/33;
        g();

        return t+q+q1+q2+q3;
}

```

-- 
Zeson
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