[llvm-dev] Virtual register defs don't dominate all uses

[Quentin Colombet via llvm-dev]

Hi Josh,

That means that at least one use of the reporter virtual register happens before its definition.
E.g.,
… = V1 <—— V1 is not defined here
V1 = … <— V1 def does not dominate all its use

Cheers,
-Quentin
> On Apr 16, 2019, at 2:47 PM, Josh Sharp via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
>  Hi all,
> I'm getting this error:  "Virtual register defs don't dominate all uses". It comes from llvm/lib/CodeGen/MachineVerifier.cpp:2138 
> I don't understand what it means. Does anyone know?
> 
> Thanks.
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev <https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190416/bf5c7ac1/attachment.html>