[llvm-dev] Errononous scheduling of COPY instruction.
Dominique Torette via llvm-dev
llvm-dev at lists.llvm.org
Thu Sep 20 08:27:28 PDT 2018
Hi,
I've instruction scheduling problem that I cannot further investigate by myself... Could someone give me some clues?
After Instruction selection, here is part of the generated instruction.
NOP
MOV_AB_ro @s1, %fab_roff0
%6:fpuaoffsetclass = COPY %fab_roff0; FPUaOffsetClass:%6
MOV_A_oo %6, def %5; FPUaOffsetClass:%6,%5
MOVSUTO_A_iSLo 24575, def %7; FPUaOffsetClass:%7
The order of instruction is very important: the COPY shall take place after the MOV_AB_ro!
But during Instruction scheduling, these two instructions have been permutated!
SU(18): NOP
SU(20): %6:fpuaoffsetclass = COPY %fab_roff0; FPUaOffsetClass:%6
SU(19): MOV_AB_ro @s1, %fab_roff0
SU(21): MOV_A_oo %6, def %5; FPUaOffsetClass:%6,%5
SU(22): MOVSUTO_A_iSLo 24575, def %7; FPUaOffsetClass:%7
I'm trying to understand why the Instruction scheduler has swapped these two instructions...
>From the trace, it seems that the Successors of SU(19) is SU(21) and not SU(20) as expected...
What kind of information between the MOV_AB_ro and COPY could be missing?
How to define that the pred of SU(20) should be SU(19)?
SU(19): MOV_AB_ro @s1, %fab_roff0
# preds left : 1
# succs left : 1
# rdefs left : 0
Latency : 0
Depth : 21
Height : 25
Predecessors:
SU(18): Ord Latency=1 Barrier
Successors:
SU(21): Ord Latency=0 Barrier
Pressure Diff :
Single Issue : false;
SU(20): %6:fpuaoffsetclass = COPY %fab_roff0; FPUaOffsetClass:%6
# preds left : 0
# succs left : 1
# rdefs left : 0
Latency : 0
Depth : 0
Height : 25
Successors:
SU(21): Data Latency=0 Reg=%6
Pressure Diff : FPUaOffsetClass -1 FPUabOffsetClass -1
Single Issue : false;
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Dominique Torette
System Architect
Rue des Chasseurs Ardennais - Liège Science Park - B-4031 Angleur
Tel: +32 (0) 4 361 81 11 - Fax: +32 (0) 4 361 81 20
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