[llvm-dev] [RFC] Array Register Files

Luke Kenneth Casson Leighton via llvm-dev llvm-dev at lists.llvm.org
Mon Oct 8 19:02:11 PDT 2018


nicolai, hi,

couple things occurred to me, after writing this out
https://libre-riscv.org/llvm_vector_backend/

(1) a way to express the link between "what's wanted" and "what's
available" is needed.  i.e. there needs to be a key-value store.  as
they stand, proposed ARF and Reg classes only express "what's
available", they don't express "what's wanted".

(2) really SV and RVV both absolutely critically require that "length"
CSR (VL) to be part of the data structures, in order for the registers
to actually be "arrays", at all.  if there is no length specified (at
the "what's wanted" level), there's no way for the backend to
determine "what's available".

(3) if the length of an array is specified as part of the data
structures, microarchitectures that don't have that concept can simply
set that to "1" in all data structures.  i *think* that means that for
AMDGPU standard vector regs, length would be 1, and for those special
shader registers, it would be 12.  or 1-12.  or whatever they had been
globally set to for the duration of the application lifetime.

(4) VL ties in with robin kruppe's intermediary representation RFC
(initially designed for RVV). i think it's important to get in touch
with him on that.

(5) the idea of unioning traditional register classes is a good one: i
would hesitate to special-case that.  if the ARF and Reg classes are
not capable of expressing the traditional register classes, i would
say that there's something wrong with how the ARF and Reg classes are
designed.

l.


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