[llvm-dev] [RFC] Implementing a general purpose 64-bit target (RISC-V 64-bit) with i64 as the only legal integer type

Friedman, Eli via llvm-dev llvm-dev at lists.llvm.org
Wed Oct 3 13:21:39 PDT 2018

On 10/3/2018 2:27 AM, Alex Bradbury via llvm-dev wrote:
> # Purpose of this RFC
> This RFC describes the challenges of modelling the 64-bit RISC-V target (RV64)
> and details the two most obvious implementation choices:
> 1) Having i64 as the only legal integer type
> 2) Introducing i32 subregisters
> I've worked on implementing both approaches and fleshed out a pretty complete
> implementation of 1), which is my preferred option. With this RFC, I would
> welcome further feedback and insight, as well as suggestions or comments on
> the target-independent modifications (e.g. TargetInstrInfo hooks) I suggest as
> worthwhile.

Having i64 as the only legal integer seems fine for a target that 
doesn't have architectural names for the 32-bit sub-registers.  (For 
targets where the 32-bit registers have different names, you would run 
into issues with constructs like inline asm.)

The target-independent changes you've listed seem minor, and 
custom-lowering float<->int bitcasts is done on a lot of targets.


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