[llvm-dev] [RFC] Tablegen-erated GlobalISel Combine Rules

[David Greene via llvm-dev]

Daniel Sanders via llvm-dev <llvm-dev at lists.llvm.org> writes:

> Unfortunately, Instruction is a class-hierachy based design with
> specialized getters for each subclass whereas MachineInstr is a single
> one-size-fits-all class. It's likely to be difficult to unify them
> with templates. A common API sounds feasible to some degree, certainly
> the G_* opcodes and the Instruction hierarchy ought to be able to
> agree on abstraction that can interact with both, and
> MachineMemOperand ought to be able to agree with
> LoadInst/StoreInst/Atomic*Inst

Yeah, that's along the lines of what I was thinking.  Long way off, of
course.  :)

> I expect it to be able to deal with ISel too. The main difference
> between the two is that ISel's apply step is required to constrain
> operands to a register class whereas Combine doesn't need to do that
> but can choose to. I'm intending to share code between the tablegen
> passes for Combine and ISel so that it will be the same underlying
> code generator.

Cool.  If combine can choose to enforce constraints, then the mechanism
is there for isel to use.

> The syntax could also work for the Legalizer, and RegBankAlloc too.

I hadn't thought about legalizer and things like RegBankAlloc.  That's
neat!  Even though legalizer is a special case, there still may be value
in making its specification more declarative.

                               -David