[llvm-dev] ARM64, dropping ADRP instructions, and ld.lld

[Tim Northover via llvm-dev]

Hi Eric,

On 21 May 2018 at 13:31, Eric Gorr via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> I am working in an embedded environment with somewhat restrictive memory
> requirements where the page alignment requirements of an ADRP instruction
> cannot be guaranteed.

It sounds like you're relying on the linker optimization hints that
Clang emits. As you've seen they're designed to allow the linker to
convert adrp/add pairs into simpler nop/ldr sequences. If it works for
your purposes, great; but bear in mind it was designed as a
microarchitectural optimization so it's not guaranteed to trigger or
be able to remove all adrps if it does.

> As near as I can determine, ld.lld does not have this same feature. I am
> wondering if I am missing something, if such a feature is being planned,

MachO support in lld is pretty immature compared to ELF and it
certainly doesn't look like it's supported yet. I'm afraid I'm not
sure about the longer-term plans.

> or if there is an alternative I have not considered yet.

Ideally this would probably be handled by implementing proper
-mcmodel=tiny support in LLVM so that only ADR instructions are
emitted in the first place (instead of leaving you with a bunch of
NOPs). In ELF-land that probably wouldn't be too hard (there are
already relocations for it in the spec), but MachO is chronically
starved of free locations so that might get very nasty very quickly.

Cheers.

Tim.