[llvm-dev] generating multiple instructions for a single pattern

[Jatin Bhateja via llvm-dev]

Other suggestions

1/ Write a separate MI pass to split the macro MI which was generated
earlier as a result of ISel to multiple MIs.
2/ Take the decision of splitting later in the pipeling during MC lowering.

Decision about when you need to split should be driven by your intent to do
any further processing over constituent instruction.

~ Jatin



On Fri, Mar 2, 2018 at 8:19 PM, Jatin Bhateja <jatin.bhateja at gmail.com>
wrote:

> Hi Nagaraju,
>
> Few suggestions split this into following steps.
>
> 1/ DAG Legalization : Custom lower the instruction (branch in your case)
> appropriately in legalization to target specific DAG nodes and glue the
> nodes together which you want scheduler should schedule together.
>
> 2/ Instruction Selection : Define patterns to match the custom DAG nodes.
>
> Thus actual decision of creating multiple instruction is taken care by
> legalizer and selection phase is dump which does pattern matching over
> whatever DAG is
> feeded to it.
>
> Thanks,
> Jatin
>
> On Fri, Mar 2, 2018 at 4:39 PM, Nagaraju Mekala via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hi All,
>>
>>    I am working on a target which requires to generated two
>> instructions for a single branch instruction.
>> ex:
>>    imm 1
>>    br r4,0xabcd
>>    branch address is 0x1abcd, imm has the upper 16 bits and br has
>> lower 16 bits.
>>
>>   Can anyone let me know how to write these kind of patterns in the
>> InstrInfo.td file.
>>
>> Thanks in Advance,
>> Nagaraju
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
>
>
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