[llvm-dev] generating multiple instructions for a single pattern

[Nagaraju Mekala via llvm-dev]

Hi All,

   I am working on a target which requires to generated two
instructions for a single branch instruction.
ex:
   imm 1
   br r4,0xabcd
   branch address is 0x1abcd, imm has the upper 16 bits and br has
lower 16 bits.

  Can anyone let me know how to write these kind of patterns in the
InstrInfo.td file.

Thanks in Advance,
Nagaraju