[llvm-dev] [SelectionDAG] lowering shifts to parts

Davis, Alan via llvm-dev llvm-dev at lists.llvm.org
Fri Jun 29 06:18:18 PDT 2018

This is what I hope is a simple question about target lowering. The target has 64 bit registers and support for some but not all 64-bit operations. It does not support 64-bit shifts. What I would like to do is have them lowered to SHL_PARTS.

In target lowering I set i64 as a legal type, since most operations are supported and we have 64 bit registers. This has the unfortunate effect of preventing type legalization from lowering the shifts to SHL_PARTS.

So I tried setOperationAction(ISD::SHL, MVT::i64, Expand), but then I get an assertion failure because apparently the expander cannot handle scalar shifts.

Is there some other way? Do I need to make a custom action? If so, can I just call ExpandIntRes_Shift(), which performs that transformation for type legalization?

More generally, is there another target that does something similar? What's the preferred approach for handling partial support for a given type?

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