[llvm-dev] Target hardware loop instruction via intrinsics

[Jon Chesterfield via llvm-dev]

Hi,

Hexagon has a MIR pass for detecting loops that map onto hardware support.
I think a similar approach would be viable for my target but am put off by
the complexity of determining whether a given loop is legal to transform.

Instead, I would like to pass the responsibility for determining legality
onto the C programmer who is assumed sufficiently familiar with the
architecture.

I think this would require a pair of intrinsics to denote the start and end
of the loop. Is there a reasonable way to model this in llvm?

If not, would anyone suggest a compiler programmer friendly, even if
application programmer hostile, way to target a loop instruction with many
constraints on validity.

Thanks!

Jon
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180621/221c56b7/attachment.html>