[llvm-dev] [RISCV] Hard float ABI and testing

Bruce Hoult via llvm-dev llvm-dev at lists.llvm.org
Fri Jun 15 13:44:23 PDT 2018

I'm in the process of ramping up to be an LLVM person at SiFive. We don't
have FP hardware on our current 32 bit CPUs so the soft float ABI is fine
there at the moment. Our 64 bit "Freedom Unleashed" cores have an FPU so
we'd love to have hard float ABI support in LLVM, but it's not at the top
of our priorities to do it ourselves. We'd be very happy if you implemented

On Fri, Jun 15, 2018 at 8:07 AM, Roger Ferrer Ibáñez via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Hi all,
> as part of our research activities, we, the Barcelona Supercomputing
> Center [1], are actively looking into RISC-V for HPC. So we are
> comitted to make sure the RISC-V LLVM ecosystem thrives in that field
> of computing, including (but not limiting to) 64-bit and vector
> support.
> Linux is pervasive in HPC and we found that the current RISC-V in LLVM
> does not support the hard float ABI used by the main distributions
> (lp64d) yet.
> Our question is about the status of this support. Is it already in the
> pipeline and waiting to be upstreamed? Or it hasn't been started yet
> by anyone. In the last case, we are interested in contributing an
> implementation.
> Also, we're planning to set up testing for the RISC-V on Linux (we're
> considering LLVM test-suite as a starting point). We wonder if there
> are other groups that have been looking into this that could share
> their experiences.
> Any other suggestions and comments are welcome, of course :)
> Kind regards,
> Roger
> [1] www.bsc.es
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