[llvm-dev] [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths

[Bruce Hoult via llvm-dev]

On Tue, Jul 31, 2018 at 9:13 PM, Renato Golin via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Indeed. I have a limited view on the spec and even more so on hardware
> implementations, but it is my understanding that there is no attempt
> to change VL mid-loop.
>
> If we can assume VL will be "the same" (not constant) throughout every
> self-contained sub-graph (from scalar|memory->vector to
> vector->scalar|memory), there we should encode it in the IR spec that
> this is a hard requirement.
>

I don't see any harm in (very occasionally) making the VL shorter somewhere
within an iteration of a loop. Some work that was already done will be
wasted, but that's not a correctness problem. Making the VL longer
mid-iteration would of course be very bad.

The important thing is that the various source and destination pointers are
updated by the correct amount at the end of the loop.


> This seems consistent with your explanation of the Cray VL change as
> well as Bruce's description of RISC-V (both seem very similar to me),
> where VL can change between two loop iterations but not within the
> same iteration.
>

I'm not sure whether it will end up being possible or not, but I did
describe two situations where at least some RISC-V implementations might
want to change VL within an iteration:

1) a memory protection problem on some trailing part of a vector load or
store, causing that iteration to operate only on the accessible part, and
the next iteration to start from the first address in the non-accessible
part (and actually take a fault)

2) an interrupt/task switch in the middle of a loop iteration. Some
implementations may want to save/restore only the vector configuration, not
the values of the vector registers.

> I don't see why predicate values would be affected at all.  If a machine
> > with variable vector length has predicates, then typically the resulting
> > operation would operate on the bitwise AND of the predicate and a
> > conceptual all 1's predicate of length VL.
>
> I think the problem is that SVE is fully predicated and Cray (RISC-V?)
> is not, so mixing the two could lead into weird predication
> situations.
>

The current RISC-V proposal has a 2-bit field in each vector instruction,
with the values indicating:

- it's actually scalar
- vector operation with no predication
- vector operation, masked by the predicate register
- vector operation, masked by the inverse of the predicate register
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