[llvm-dev] RFC: What is the real behavior for the minnum/maxnum intrinsics?

[Matt Arsenault via llvm-dev]

> On Jul 26, 2018, at 18:51, Stephen Canon via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> ARMv8:
> 1. FMIN / FMAX implement the new minimum / maximum exactly.
> 2. FMINNM / FMAXNM implement minimumNumber / maximumNumber if we can prove no sNaNs are present. If sNaN may be present, we need to canonicalize each argument first.
> 

The AMDGPU instructions in the default mode for compute match #2 here. They also do seem to preserve the new signed 0 behavior.

If we can settle on stating explicitly the in the LangRef that de-facto current behavior where the signalingness of a NaN is ignored here, that would allow solving my immediate problems. The required lowering code would be clear and optimizable. This isn’t ideal but at as far as the current standard is concerned, this fits with sNaN being generally broken in LLVM (e.g. constant folding for every operation doesn’t bother quieting them)

This is the only part that I immediately care about. When the new standard is finalized, we can re-visit the other details such as the signed 0 question. Are there any targets that don’t already treat -0.0 as < 0.0?

-Matt
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