[llvm-dev] [RISCV][PIC] Lowering pseudo instructions in MCCodeEmitter vs AsmPrinter

[Roger Ferrer Ibáñez via llvm-dev]

Hi,

thanks a lot Eli.

Now I see that the relocmodel is not the right piece of information needed
here but the target flags (when coming from the backend) and the variant
kind (when coming from the assembler). Looks like the former should be
somehow lowered to the latter, does this make sense?

Kind regards,

2018-07-10 20:08 GMT+02:00 Friedman, Eli <efriedma at codeaurora.org>:

> On 7/10/2018 9:51 AM, Roger Ferrer Ibáñez via llvm-dev wrote:
>
>> H all,
>>
>> I'm looking at generating PIC code for RISC-V in the context of Linux.
>> Not sure if anyone is working on this already, any inputs are very welcome.
>>
>> I'm now looking at function calls which in the RISCV backend are
>> represented via two pseudoinstructions RISCV::TAIL and RISCV::CALL.
>>
>> Currently those pseudos are lowered in MCCodeEmitter. They are expanded
>> into AUIPC and JALR instructions and the first one needs a relocation,
>> which for a static reloc model is R_RISCV_CALL but for PIC code should be
>> R_RISCV_CALL_PLT.
>>
>
> This is not really correct.  A direct call is represented using
> R_RISCV_CALL; a call through a PLT is represented with R_RISCV_CALL_PLT.
> In a static relocation model, no calls use the PLT; with a PIC relocation
> model, some, but not all, calls use the PLT.
>
> In assembly, this is represented by changing the operand of the call
> instruction: a direct call is "call f", a call through the PLT is "call
> f at plt". In the MC layer, this is represented using
> MCSymbolRefExpr::VK_PLT.  In the LLVM backend, this is represented with a
> target-specifc flag (for example, X86II::MO_PLT).
>
> -Eli
>
> --
> Employee of Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux
> Foundation Collaborative Project
>
>


-- 
Roger Ferrer Ibáñez
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