[llvm-dev] [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths

[David A. Greene via llvm-dev]

Robin Kruppe <robin.kruppe at gmail.com> writes:

> Everything else I know of that falls under "changing vector lengths"
> is better served by predication or RISC-V's "active vector length"
> (vl) register.

Agreed.  A "vl" register is slightly more efficient in some cases
because forming predicates can be bothersome.

I also want to caution about predication in LLVM IR.  The way it's done
now is, I think, not quite kosher.  We use select to represent a
predicated operation, but select says nothing about suppressing the
evaluation of either input.  Therefore, there is nothing in the IR to
prevent code motion of Values outside the select.  Indeed, I ran into
this very problem a couple of months ago, where a legitimate (according
to the IR) code motion resulted in wrong answers in vectorized code
because what was supposed to be predicated was not.  We had to disable
the transformation to get things working.

Another consequence of this setup is that we need special intrinsics to
convey evaluation requirements.  We have masked
load/store/gather/scatter intrinsics and will be getting masked
floating-point intrinsics (or something like them).

Years ago we had some discussion about how to represent predication as a
first-class IR construct but at the time it was considered too
difficult.  With more and more architectures turning to predication for
performance, perhaps it's time to revisit that conversation.

                               -David